Title:
STATIC RAM
Document Type and Number:
Japanese Patent JPS5774884
Kind Code:
A
Abstract:
In a static RAM fully asynchronous active equilibration and pre-charging of the RAM's bit lines (24) provides improved memory access time and lower active power dissipation. Each change in the memory's row (34) address is sensed for developing a clock pulse (50) of a controlled duration. The clock pulse (50) is received by a group of equilibrating transistors (46) and a group of pre-charging transistors (46) which are coupled to the memory's bit lines. When the clock pulse (50) occurs, all the above-mentioned transistors (46) conduct to effect simultaneous equilibration and pre-charging of the bit lines (24).
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Inventors:
RAAURU SUDO
KIMU KAABAA HAADEII
JIYON DEII HAITORII
KIMU KAABAA HAADEII
JIYON DEII HAITORII
Application Number:
JP9979981A
Publication Date:
May 11, 1982
Filing Date:
June 29, 1981
Export Citation:
Assignee:
INMOS CORP
International Classes:
G11C11/41; G11C11/419; (IPC1-7): G11C11/34
Domestic Patent References:
| JPS5619587A | 1981-02-24 | |||
| JPS54152931A | 1979-12-01 | |||
| JPS5451736A | 1979-04-23 | |||
| JPS554735A | 1980-01-14 |
Foreign References:
| US4099265A | 1978-07-04 |