PURPOSE: To obtain the clocked CMOS frequency divider operated at a higher speed than that of a dynamic type frequency divider regardless of the static type frequency divider.

CONSTITUTION: A memory function by inverters V1, V2 or V3, V4 is added to two high speed dynamic frequency dividers being a dynamic frequency divider comprising CL1, CL2 and other dynamic frequency divider comprising CL3, CL4. Thus, the static operation compatible with a low speed operation is attained and the output data of each frequency divider are used for other input data by cross-coupling to reduce the number of gates included in a path (critical path) whose signal propagation delay time is longest.