PURPOSE: To enhance a static-type semiconductor memory in resistance to soft error and a cell peripheral circuit in operation speed by a method wherein the coupling capacitance of a memory cell drive transistor is set larger than that of a transistor in a cell peripheral circuit.

CONSTITUTION: A polycrystalline silicon film deposited on all the surface of a substrate 1 is anisotropically etched to leave side walls 6a and 6b to gate electrodes 4a and 4b. Then, for instance As+ ions are implanted into the substrate 1 for the formation of a high concentration N+ diffusion region in a drain region. In succession, photoresist is applied on all the surface of the substrate 1, and a photoresist pattern 7 is left only on a drive MOS transistor region. Then, the exposed gate electrode side wall 6b of a MOS transistor in a cell peripheral circuit is removed by isotropic etching. After the photoresist pattern 7 is removed, the implanted As+ ions are activated to form the drain and source region of a MOS transistor.