Title:
STEREO MULTIPLEX SIGNAL DECODING CIRCUIT
Document Type and Number:
Japanese Patent JPS63169138
Kind Code:
A
Abstract:
Arrangement for decoding a stereo multiplex signal, comprising a baseband stereo signal (L+R), a stereo difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier and a pilot signal located between the frequency bands of the said two signals, said arrangement having an input for the stereo multiplex signal and left and right stereo signal outputs, said input being coupled at one end via a pilot selection circuit to a phase-locked loop for regenerating the sub-carrier and at the other end to a multiplier circuit for multiplying at least the modulated stereo difference signal by the regenerated sub-carrier. In order to improve the stereo channel separation the pilot selection circuit comprises a bandpass filter of the switched capacitor type a clock input of which is coupled to an output of a voltage-controlled oscillator incorporated in the loop. A mono-stereo control can be realised therein in a simple manner by varying the phase transfer of the last-mentioned bandpass filter at least at the pilot frequency in dependence upon a mono-stereo control signal.
Inventors:
ARUTOURU HERUMANUSU MARIA FUAN
Application Number:
JP32159787A
Publication Date:
July 13, 1988
Filing Date:
December 21, 1987
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H04H20/88; H03D1/22; H03H19/00; H04B1/16; (IPC1-7): H04H5/00
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)