PURPOSE: To synthesize a complete interlace reproducing signal by switching a reproducing video signal and a 0.5H delay signal basing on a switching control signal which is inverted by field synchronization in the recording and reproducing start and final ends to obtain a prescribed level at all times in an equivalent pulse section.

CONSTITUTION: A counting output is derived from a counter 8 having an automatic frequency control output (e) as a counting input and uses a vertical synchonizing separating pulse (d) as a reset input. An FF circuit 9 is set by rise of an AND output (b) and is reset by an output (g). An output (i) of the FF9 rises immediately before the recording start and final ends, and this rise part is divided by a 1/2 frequency-dividing circuit 10. An FF circuit 11 which uses the output (g) as a reset input and uses an output (j) as a set input derives an output land l' which always become a low level in an almost equivalent pulse section. The output controls a switch 2a and the inverted output of this output controls a switch 2b.