Title:
SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME
Document Type and Number:
Japanese Patent JP3236156
Kind Code:
B2
Abstract:
PURPOSE: To obtain a semiconductor memory accelerating sense operation at a low voltage time and operating at a high speed with a low voltage by adjusting the operation timing of a sense amplifier drive signal.
CONSTITUTION: By driving a transistor 9 with a large current supply ability by a signal SEN1, the potential of the signal SAN is made to be at a low level, and the bit line potential of the low level side is lowered at a high speed. Roughly simultaneously, the transistor 15 with a small current supply ability dispersedly arranged in a word line lining area between memory blocks is driven by the signal SEP1, and the potential of a high level side is held so as not to be lowered. Thereafter, the transistor 10 with a large current supply ability is driven by the signal SEP2, and the potential of the signal SAP is made to be at a high level, and the bit line potential of the high level side is raised at a high speed. By such a operation timing, the sense operation at the low voltage is accelerated.
Inventors:
Yoshitaka Mano
Akinori Shibayama
Motomochi Kenji
Wataru Abe
Akinori Shibayama
Motomochi Kenji
Wataru Abe
Application Number:
JP33712993A
Publication Date:
December 10, 2001
Filing Date:
December 28, 1993
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/409; G11C11/401; (IPC1-7): G11C11/409
Domestic Patent References:
| JP60136993A | ||||
| JP316082A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)
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