Title:
MATRIX ARITHMETIC OPERATION CIRCUIT
Document Type and Number:
Japanese Patent JP3231811
Kind Code:
B2
Abstract:
PURPOSE: To form the matrix arithmetic operation circuit with less capacity of a ROM and to attain the arithmetic operation at a high operating speed by receiving an optical k-dimension binary vector (x) and outputting the product between the vector and a binary matrix H of m-row and k-column having specific values as the result of arithmetic operation.
CONSTITUTION: A ROM 11 has j-areas, and all products Hi.xi between a partial vector xi whose degree is k/j and a partial matrix Hi and written in advance to an i-th area. An optional k-dimension binary vector (x) with which products with j-sets of partial matrices Hi is decomposed into vectors xi and the result is inputted to an address bus of the ROM 11 together with its vector number (i). The product Hi.xi with respect to the inputted vector xi and the address (i) is outputted to the data bus. An EOR circuit 12 forms a loop with a register 13 whose size is k/j and the EXOR sum from (i) equals to 1 to (j) of the data bus output Hi.xi in the ROM 11 expressed in equation I is calculated and the result is outputted as a product P between the matrix H and the k-degree binary vector (x). In the equation I, (+)Σ indicates the binary sum of EXOR.
Inventors:
Douguchi Masato
Kenzo Urabe
Kenzo Urabe
Application Number:
JP24237191A
Publication Date:
November 26, 2001
Filing Date:
August 29, 1991
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
G06F11/10; H03M13/00; H03M13/15; H03M13/37; (IPC1-7): H03M13/37; G06F11/10; H03M13/15
Domestic Patent References:
| JP63291108A | ||||
| JP2273867A | ||||
| JP311465A | ||||
| JP214817B2 |
Other References:
Ｈａｒｒｙ Ａ．Ｎｉｅｎｈｏｕｓ ｅｔ．ａｌ．”Ａ Ｐａｒａｌｌｅｌ ＳＲＴ ｄｉｖｉｄｅｒ ｆｏｒ ｓｙｓｔｏｌｉｃ ｌｉｎｅａｒ ｓｙｓｔｅｍ ｓｏｌｖｅｒｓ”ＩＥＥＥ ｐｒｏｃｅｅｄｉｎｇｓ １９８９ ｓｏｕｔｈｅａｓｔｃｏｎ ｐｐ．１３６１−１３６５
Attorney, Agent or Firm:
Manabu Otsuka