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Title:
記憶回路および制御方法
Document Type and Number:
Japanese Patent JP5298644
Kind Code:
B2
Abstract:
A memory circuit having a global signal driving circuit, which, when a first read signal is inputted from a first bit signal line with a column signal inputted from a column signal line, outputs the first read signal as a global signal from a global signal line, and, when a first driving write signal is inputted from the first bit signal line, inhibits the first driving write signal from being outputted to the global signal line on the basis of a first write signal inputted from a first write signal line.

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Inventors:
Seiji Murata
Application Number:
JP2008141854A
Publication Date:
September 25, 2013
Filing Date:
May 30, 2008
Export Citation:
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Assignee:
富士通株式会社
International Classes:
G11C11/413; G11C11/417
Domestic Patent References:
JP2002100188A
JP2000207886A
JP2007273007A
JP2005025859A
JP2007213732A
Foreign References:
WO2005024838A1
Attorney, Agent or Firm:
Yu Sanada
Masahisa Yamamoto



 
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