To obtain rendering which is made fast by composing a storage device using a plurality of system of pixel arithmetic-logic units(ALUs) which are coupled with a pixel buffer, an input/output data formatter, and a read/write data formatter.

Input graphics data are demultiplexed by an input data demultiplexer 126, and transferred to the input data formatter 130 through an input data bus 128 and formatted, and the data are transmitted to pixel ALUs 120 and 121 for processing through input data buses 129 and 131. The data are formatted by a formatter 140 from a pixel ALU to an SRAM and allocated to an SRAM pixel buffer 118 through a data bus 141. The SRAM pixel buffer 118 reads out the data formatted by the formatter 140 from the pixel ALU to the SRAM through a pixel ALU data bus 138.