Title:
記憶装置
Document Type and Number:
Japanese Patent JP7361730
Kind Code:
B2
Abstract:
A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.
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Inventors:
Shuhei Nagatsuka
Tatsuya Onuki
Kiyoshi Kato
Shunpei Yamazaki
Tatsuya Onuki
Kiyoshi Kato
Shunpei Yamazaki
Application Number:
JP2020568866A
Publication Date:
October 16, 2023
Filing Date:
November 18, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C5/02; G11C5/04; G11C11/405; H01L21/336; H01L21/8234; H01L27/06; H01L27/088; H01L29/786; H01L29/788; H01L29/792; H10B12/00
Domestic Patent References:
| JP200971313A | ||||
| JP2015181159A | ||||
| JP201482357A | ||||
| JP2018195794A | ||||
| JP201897907A |