PURPOSE: To discriminate whether data error is caused by the fault of a refresh (RF) control and storage part control system or of a storage part by monitoring the operational states of an RAS signal and a CAS signal in the RF control system.

CONSTITUTION: Since an edge detection circuit 1 turns an RF start signal 104 to 1 when an under-RF signal 102 is logic 1 and the CAS signal 101 is changed from 0 to 1 while the RAS signal is 0, 1 is set to an F/F 2. When the RAS signal 100 is changed from 0 to 1, the circuit 1 turns an RAS before/after detec tion signal 106 to 1 and in an AND gate 3, however, since an RF end signal 106 from the circuit 1 is 0 even after an output signal 107 from the F/F 2 is 1, 0 is outputted as an AND gate output signal 109. In an AND gate 4, since a signal 108 is 0 even after the signal 106 is turned to 1, 0 is outputted as an output signal 110. Zero is outputted from an OR gate 5 as an error detection signal 111, and error is not detected. When the content of the F/F 2 is 0 and the signal 106 is changed from 0 to 1, the signal 110 is turned to 1 and the generation of error is announced.