PURPOSE: To perform address control simply and surely, by performing required control through the movement of memory address until it is in agreement with the reference address in matching with the data segment movement in a loop.

CONSTITUTION: Addresses which are set to the 1st and 2nd address memory means 21, 22 formed with shift registers SR1, SR2WSR4 corresponding to a large and a small subminor loops 11, 12 and are sequentially incremented, and reference addresses are compared at comparators CP1, CP2, and the reference addresses are moved near a swap gate 10 of a loop 12, and a high level coincidence output is produced from the comparator CP2. Then, a gate 10 is open via a swap control means 24. At the same time, the content of the register SR2 is shifted to the register SR1 via a gate means 25 and a shift clock generating means 26, and the gate 10 is closed via the means 24 with the content coincidence signal between the reference address and the register SR1 at the comparator CP1, and the address control to perform high speed processing with the address shifted to the loop 11 can be made simply and surely.