PURPOSE: To transfer the store data of a next instruction to an idle source data register without queuing time by providing a circuit to select a store data register and selecting an idle store data register.

CONSTITUTION: At the transfer process of an A instruction, data 1 transferred first to a main memory 14 are transferred from a store data register 4, the store data register 4 is idle, and then, a store data register selecting circuit 5 outputs a next instruction store data transfer permitting signal to an instruction control part 15. By this signal a B instruction is started to execute. Data (i) and (m) are respectively read from a local storage 13 to an arithmetic input register X16 and an arithmetic input register Y17, added by a computing element 18 and adding result data 5 are transferred to an arithmetic result register 6. When the adding result data 5 are transferred to DB7 after one arithmetic cycle, the store data register selecting circuit 5 sets the register 4 to complete to transfer first and data of an A instruction to the main memory 14 to a storing store data register number register 11 and stores the data 5.