PURPOSE: To read data out of a memory successively at a certain period.
CONSTITUTION: This controller is equipped with a memory controller 1 which specifies row and column addresses successively at the certain period and DRAMs 3 and 4 out of which data can be read at a high speed from addresses of the 1st column in respective rows by specifying both the addresses of the row and column and from the address of the 2nd column by specifying only the column address. Data in addresses of a (2n)th row are delayed by two cycles of a system clock CLK through a register group 9 and led to a multiplexer 10 and after the final data D511 of the (2n)th row is outputted, starting data D512, D513,... of an (2+1)th row are led to the multiplexer 10 without being passed through the register group 9.
SASAKI HAJIME
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