PURPOSE: To guarantee accurate control and to realize access control with low power consumption in a STRAM controller controlling STRAM.
CONSTITUTION: A RAM clock control circuit 23 and a gate means 24 are provided in accordance with respective STRAM constituting a bank. The RAM clock control circuit 23 is provided with a generation means 26 generating a control pulse signal having the pulse width of time required for the access processing of STRAM when an access request is given to STRAM of a self circuit and an issue means 27 issuing a pseudo access request to the generation means 26 when a fetch request to other STRAM is given. A gate means 24 makes a RAM clock pass through so as to supply it to STRAM when a control pulse signal is generated by setting a RAM clock given to STRAM to be input and using the control pulse signal which the generation means 26 generates as a control signal.
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KODATE MIKIKO
