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Title:
STRESS ANALYSIS SYSTEM FOR DESIGNING SEMICONDUCTOR PACKAGE AND ITS METHOD
Document Type and Number:
Japanese Patent JPH07333076
Kind Code:
A
Abstract:

PURPOSE: To achieve an analysis using a plurality of models and finite element method simultaneously by providing a model for analysis and a material constant file for each type of semiconductor package.

CONSTITUTION: When, for example, TWSOP(Thin Small Outline Package with Window, DIP type) package type is specified, it is possible to perform such editing as the additional input, rewriting, and deletion of a file where a fundamental model or a typical method of the fundamental model is registered and is also possible to store the created analysis model as one of the fundamental models and to re-utilize it. Also, when creating a plurality of models by changing dimensions, a plurality of models can be specified simultaneously by the number of rows by writing figures for a plurality of method requirements such as a line (e) and a line (i) at a line for entering dimensions. Therefore, it is not necessary to repeat creating models and the change in stress due to the change in designing requirements such as dimensions can be examined at a time.


Inventors:
ISHIBASHI MASAHIRO
Application Number:
JP12342294A
Publication Date:
December 22, 1995
Filing Date:
June 06, 1994
Export Citation:
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Assignee:
NEC CORP
International Classes:
G01L1/00; G06F17/50; H01L21/66; (IPC1-7): G01L1/00; G06F17/50; H01L21/66
Domestic Patent References:
JPH064630A1994-01-14
JPH0666696A1994-03-11
JPS6467320A1989-03-14
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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