Title:
積層メモリアレイを含む構造体
Document Type and Number:
Japanese Patent JP6518779
Kind Code:
B2
Abstract:
Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
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Inventors:
Andrea Redaelli
Application Number:
JP2017544894A
Publication Date:
May 22, 2019
Filing Date:
December 22, 2015
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
H01L21/8239; H01L27/105; H01L45/00
Domestic Patent References:
| JP2010232214A | ||||
| JP2002118306A | ||||
| JP2013058521A | ||||
| JP2010040820A | ||||
| JP2009239148A | ||||
| JP2012253148A |
Foreign References:
| US20130256625 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Nomura Yasuhisa
Nomura Yasuhisa