PURPOSE: To enable latent failure existent in inner element parts which have no continuity with power source wirings to be removed by an accelerated deterioration test in an LSI static BT.

CONSTITUTION: A target circuit element on an LSI chip is provided with an inner element bias impressing terminal so as to be exposed on the passivation film. This is overlaid with a mold resin: this resin is perforated, and holes are filled with gelled resin caps 16. By this device constitution, a target circuit element is impressed with bias via the inner element bias impressing terminal by an inner element bias impressing electrode 13 in the socket during static BT. This enables accelerated deterioration of latent failure. When the inner element bias impressing electrodes is removed after BT, the electrode of the inner element bias impressing terminal is coated again by flexibility of the gelled resin cap 16 and protected from the outer atmosphere. This causes no deterioration in moisture resistance as well.