Title:
STRUCTURE FOR INTERCONNECTING SEMICONDUCTOR REGIONS AND FABRICATION METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3398428
Kind Code:
B2
Abstract:
PURPOSE: To reduce the number of metallizations required for an intricate integrated circuit in a semiconductor device having a lateral interconnection formed of a semiconductor quantum well significantly by employing a semiconductor material for the interconnection.
CONSTITUTION: A quantum well interconnection 17 is formed through exitaxial deposition of a second material type on a layer covering the exposed layer of a substrate 10. The quantum well interconnection 17 is substantially coated with a layer of a wide band gap material forming a barrier region 21. The quantum well interconnection is formed similarly of a material having composition different from that of a semiconductor device to be formed on a same horizontal plane. Subsequently, an electrode is formed and coupled with each quantum well interconnection which is then coupled with a bias voltage.
Inventors:
Herbert goronkin
Jun Shen
Said Tailani
Raymond Kay Tsui
X Theodore Zoo
Jun Shen
Said Tailani
Raymond Kay Tsui
X Theodore Zoo
Application Number:
JP22390093A
Publication Date:
April 21, 2003
Filing Date:
August 18, 1993
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
H01L21/20; H01L23/535; H01L29/06; H01L29/80; (IPC1-7): H01L21/20; H01L29/06; H01L29/80
Domestic Patent References:
| JP5315597A | ||||
| JP595106A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi (2 outside)
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