PURPOSE: To avoid the occurrence of a hold time infringing artifact which is an error occurring in an emulation circuit having a relatively complicated clock structure by introducing a delay to a data path between storing steps of different clocks.
CONSTITUTION: A hold time infringing artifact is eliminated by assigning delay enforcement. The delays of connection delaying elements 1407 and 1408 introduced by an emulation circuit are generally smaller than the delay of switch line connection. Since the large delay of a connecting element 1404 is introduced by using the delaying element between chips passed through an un-clocked FPGA and by connecting a data path 1403 with a switch line, the difference between connection delays in clock signals is considerably smaller than the connection delay in the data path. Namely, the delay enforcement prevents the occurrence of the hold time infringing artifact between storing steps 1401 and 1402 by supplying a sufficiently large delay to the data path 1403.
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ROBAATO JIEI KOU
JIYONGUTEINGU RII
TOOMASU BII FUANGU
MINGUYANGU WANGU
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