Title:
STRUCTURE AND METHOD FOR FABRICATING STRUCTURE FOR RECEIVING FIRST AND SECOND SEMICONDUCTOR DIES
Document Type and Number:
Japanese Patent JP2011082533
Kind Code:
A
Abstract:
To provide a printed circuit board that accommodates a plurality of dies and forms wiring while being reduced in parasitic property, improved in effective heat dissipation, reduced in inductance, and enabled in grounding at low resistance.
A structure further includes: a printed circuit board 898 mounted to a bottom 825 of a substrate 820; and at least one via 827 in the substrate. A first substrate bond pad 822 is connected to a first signal bond pad 826 of a first semiconductor die 810 via a first signal bonding wire 814, and at least one via electrically connects the first substrate bond pad and the printed circuit board.
Inventors:
HASHEMI HASSAN S
COTE KEVIN J
COTE KEVIN J
Application Number:
JP2010249494A
Publication Date:
April 21, 2011
Filing Date:
November 08, 2010
Export Citation:
Assignee:
SKYWORKS SOLUTIONS INC
International Classes:
H01L23/12; H01L23/36; H01L25/04; H01L23/367; H01L23/498; H01L23/64; H01L25/065; H01L25/18
Domestic Patent References:
| JPH08172141A | 1996-07-02 | |||
| JPH0955459A | 1997-02-25 | |||
| JPH09283700A | 1997-10-31 | |||
| JPH05343556A | 1993-12-24 | |||
| JPH0582717A | 1993-04-02 | |||
| JPH08255868A | 1996-10-01 |
Foreign References:
| WO2000049657A1 | 2000-08-24 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai