SUB-MOUNT FOR OPTICAL SEMICONDUCTOR ELEMENT

Title:

SUB-MOUNT FOR OPTICAL SEMICONDUCTOR ELEMENT

Document Type and Number:

Japanese Patent JPH06326210

Kind Code:

A

Abstract:

PURPOSE: To prevent die bonded solder from coming into contact with a junction exposed to a chip side especially when assembling J/D required for low temperature characteristics.

CONSTITUTION: Barrier layers 7a and 7b are formed on both surfaces of a sub-mount board 10. Furthermore, an AuSn eutectic solder layer 8 is partially formed on the barrier layer 7b where an AuSn eutectic solder layer 9 is installed to the whole surface of the barrier layer 7b. This construction makes it possible to inhibit the amount of solder which swells out to a chip side to a satisfactory extent, thereby providing a high reliability laser element which reduces an initial failure attributable to soldering short to a junction and which is virtually immune to the effect of solder in an environmental test.

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Inventors:

ISHII MITSUO

Application Number:

JP11146693A

Publication Date:

November 25, 1994

Filing Date:

May 13, 1993

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP

International Classes:

H01L21/52; H01L23/12; H01L33/62; H01S5/00; (IPC1-7): H01L23/12; H01L21/52; H01L33/00; H01S3/18

Attorney, Agent or Firm:

Kenichi Hayase

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