Title:
SUBSCRIBERY LINE CONTROLLER
Document Type and Number:
Japanese Patent JP3717635
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the processing load of firmware regardless of the increase of a subscriber line by providing firm ware for periodically monitoring a flag indicating the change of signal data indicating the state of the subscriber line displayed by a displaying means.
SOLUTION: SCAN signal data obtained by scanning a subscriber circuit are inputted to a comparator circuit 104. Previously stored (Last-Look) SCAN signal data are read from an SCAN memory 121 to the comparator circuit 104, and latched by an SCAN signal latch circuit 105. The SCAN signal data are compared with the output of the latch circuit 105, and the result is transmitted to a writing control circuit 111 for controlling the writing of an SCAN memory 121 and a writing controlling circuit 112 for controlling the wiring of an SCAN change flag memory 122. Then, when incoincidence between the (Last-Look) SCAN signal data and the received SCAN signal data is detected, a change flag is turned into on '1', and the data of the SCAN memory 121 are updated.
Inventors:
Nao Koga
Application Number:
JP18656497A
Publication Date:
November 16, 2005
Filing Date:
July 11, 1997
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04M3/00; H04Q1/02; H04Q3/42; H04M3/30; H04Q3/72; H04M3/22; (IPC1-7): H04Q3/72; H04M3/30; H04Q3/42
Domestic Patent References:
| JP59003076B1 | ||||
| JP6252939A |
Attorney, Agent or Firm:
Hayashi Tsunetoku
Kenji Doi
Kenji Doi
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