Title:
SUBSTRATE ARCHITECTURE FOR SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGE STRUCTURES
Document Type and Number:
Japanese Patent JP2019068043
Kind Code:
A
Abstract:
To solve the problem in which package performance may be impacted by such issues as package warpage and poor solder joint formation in assembly processes utilized in assembly of microelectronic package structures such as package on package (PoP) structures.SOLUTION: Methods and structures include: a first substrate 102 comprising a first die 104, where an underfill material 115 is disposed on a first surface of the first substrate adjacent to the first die; and a second substrate 108 disposed on the first substrate, where the second substrate comprises at least one opening 116 disposed over the first die, where the at least one opening is at least partially filled with the underfill material.SELECTED DRAWING: Figure 1
Inventors:
THOMAS DE BONIS
ROBERT NICKERSON
NITIN DESHPANDE
OMKAR KARHADE
ROBERT NICKERSON
NITIN DESHPANDE
OMKAR KARHADE
Application Number:
JP2018125319A
Publication Date:
April 25, 2019
Filing Date:
June 29, 2018
Export Citation:
Assignee:
INTEL CORP
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2013069942A | 2013-04-18 | |||
| JP2008166373A | 2008-07-17 | |||
| JPH11312712A | 1999-11-09 | |||
| JP2013062274A | 2013-04-04 |
Foreign References:
| US20110176280A1 | 2011-07-21 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation