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Patent Searching and Data


Title:
SUBSTRATE FOR MOUNTING SEMICONDUCTOR CHIP AND METHOD FOR MOUNTING SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JPH1041615
Kind Code:
A
Abstract:

To increase the junction strength between a semiconductor chip and a board not only by joining junction lands formed on the board for mounting a semiconductor chip and electrodes formed on the semiconductor chip but also by forming, on the board for mounting a semiconductor chip, a land for securing the strength to be joined to a non-operating electrode formed on the semiconductor chip and joining these to each other.

On a circuit forming face 1a of a semiconductor chip 1, a non-operating electrode 105 exists an usual that is an electrode for a unit test of a semiconductor chip that has nothing to do with the function of the semiconductor chip after the chip is mounted. In correspondence with the non-operating electrode 105, a land 103 for securing the strength which is not electrically connected to a wiring on a circuit board where a board 104 for mounting a semiconductor chip is to be mounted is formed on a semiconductor chip mounting face 4a of the board 104. Electrode terminals 13 and a junction land 102 are joined to junction materials 7 through bumps 6 and the non-operating electrode 105 and the land 103 securing the strength are also joined to a junction material 7 through a bump 6. By this method, the number of junction points increases and thereby the junction strength can be increased.


Inventors:
OTANI HIROYUKI
YAGI TAKAHIKO
YAMAMOTO KENICHI
Application Number:
JP19050596A
Publication Date:
February 13, 1998
Filing Date:
July 19, 1996
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/44; H01L21/48; H05K3/34; H01L21/50; H01L21/60; H01L23/498; H05K1/18; (IPC1-7): H05K3/34; H05K1/18
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)