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Title:
SUBSTRATE PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP2004128383
Kind Code:
A
Abstract:

To provide a substrate processing system capable of compensating for the reduction in the cooling efficiency in a vacuum.

In a multi-chamber CVD system provided with a CVD chamber applying CVD to a wafer 1 and a transfer chamber 11 with a wafer mount device 18 installed thereon, when a high-temperature wafer 1 is carried from the CVD chamber to a cooling chamber 14 via the transfer chamber 11 by means of a tweezer 18a of the wafer mount device 18, the wafer 1 is carried while approaching the ceiling face of the transfer chamber 11 so as to efficiently dissipate the heat of the wafer to the ceiling face only with radiation thereby efficiently cooling the wafer 1 during the transfer. Cooling in advance the wafer at a high cooling efficiency during the transfer compensates for a deficiency in the cooling capability of only the radiation so as to reduce the time until the wafer is cooled to a desired temperature even when the cooling chamber has the same degree of vacuum as that of the transfer chamber and to prevent a deterioration in the throughput, the performance and the reliability or the like.


Inventors:
YASUI TAKESHI
Application Number:
JP2002293473A
Publication Date:
April 22, 2004
Filing Date:
October 07, 2002
Export Citation:
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Assignee:
HITACHI INT ELECTRIC INC
International Classes:
H01L21/677; H01L21/31; H01L21/68; (IPC1-7): H01L21/68; H01L21/31
Attorney, Agent or Firm:
Kajiwara Tatsuya