Title:
SUCCESSIVE APPROXIMATION CIRCUIT
Document Type and Number:
Japanese Patent JPH08251028
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To reduce an error and to make noise low by allowing a bit control circuit to adjust current output bits in response to a comparison signal by using a control value and compensating an error due to a through rate. SOLUTION: A successive approximator circuit 12 has a bit conversion control circuit 23 and an FF circuit 34. The conversion control circuit 24 of the circuit 23 traces the current state in successive approximation cycles. The bit control circuit 30 generates the control value in response to a control signal and the comparison signal 20 and the circuit 30 controls the circuit 34 to generate 1st output bits 38, which are fed back to the circuit 30. Then the circuit 30 adjust the said output bits in response to the comparison signal and output bits and compensate the error due to the through rate to correct the last estimated value. Then the circuit 34 generates next output signals as digitally approximated variation signals.
Inventors:
JIEFURII POORU GURANDOBUIGU
DEBUITSUDO JIERAADO BUARANKOOT
DEBUITSUDO JIERAADO BUARANKOOT
Application Number:
JP34002595A
Publication Date:
September 27, 1996
Filing Date:
December 04, 1995
Export Citation:
Assignee:
AT & T CORP
International Classes:
H03M1/38; H03K23/00; H03M1/06; H03M1/46; (IPC1-7): H03M1/38; H03K23/00
Attorney, Agent or Firm:
Hirofumi Mimata