PURPOSE: To reduce the area of a circuit and to accelerate conversion speed by performing only the setting of a bit at a part having meaning in a conversion result.

CONSTITUTION: In a constitution in which a successive approximation type register 3, a timing counter 4A, an output circuit 9, and a D/A converter 5 are composed of eight bits, respectively, and when it is recognized that no input can exceed 63 LSBs in advance, the output R8 and R7 of the successive approximation type register are not set-compared, therefore, conversion time can be shortened. Also, when input is provided with a full scale of LSBs, however, it is enough to prepare the resolution of two LSBs, the output D of the successive approximation type register can be set at either '0' or '1', thereby, no setting of an R1 is required. Therefore, by setting '1' on the data E of the output number of bits and the data F of LSB position, respectively, no set comparison of the R1 is performed. In such a manner, the conversion time can be shortened.