Title:
SUCCESSIVE COMPARISON A/D CONVERTER
Document Type and Number:
Japanese Patent JP3896717
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform A/D conversion without generating charge omission from a load capacity circuit and the erroneous injection of charges at the time of a successive comparison operation and to perform the A/D conversion at high speed in a successive comparison A/D converter of a charge redistribution type.
SOLUTION: This A/D converter charges (sampling) electrical charges corresponding to the potential difference of analog input signals Vin and a reference potential Vref to all capacitors inside the load capacity circuit, then performs successive comparison control for establishing which one of a positive electrode side power supply line AVDD and a negative electrode side power supply line AVSS is to be a connection destination for the open end of the respective capacitors in the order from the capacitor of a large capacity and obtains the A/D conversion value of Vin. In this case, before a sampling operation, whether or not Vin is larger than an intermediate potential Vo between the power supply lines AVDD and AVSS is discriminated, and based on the discrimination result, the reference potential Vref is set to a first potential VH higher than the intermediate potential Vo when Vin>Vo and the reference potential Vref is set to a second potential VL lower than the intermediate potential Vo when Vin≤Vo.
Inventors:
Takahiro Yanagi
Application Number:
JP3282899A
Publication Date:
March 22, 2007
Filing Date:
February 10, 1999
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H03M1/14; H03M1/44; (IPC1-7): H03M1/14; H03M1/44
Domestic Patent References:
| JP1117543A | ||||
| JP6169217A | ||||
| JP5741032A | ||||
| JP1202925A |
Attorney, Agent or Firm:
Tsutomu Adachi