PURPOSE: To decrease the nonlinarity error of a successive comparison type A/D converter by making the delay characteristic of an output signal of a D/A converter constant independently of the output voltage.

CONSTITUTION: The switching operation is controlled for analog switches SW1∼SWn is controlled by a digital signal from a successive comparison register and a control logic circuit 4, a prescribed connecting point is selected to output an output voltage V0 corresponding to the digital signal. Then the size of transistors employed in the analog switches SW1∼SWn is designed so that the delay characteristic of the output signal is made nearly constant independently of the quantity of the output voltage V0 corresponding to the connecting point of the series resistor circuit 8. Thus, the nonlinearity error of the successive comparison type A/D converter is reduced.