Title:
SUCCESSIVE COMPARISON TYPE ANALOG/DIGITAL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JP3857450
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To correct a change component in the reference voltage of a digital/ analog(D/A) converting circuit and to simplify a circuit configuration by providing plural capacitor circuits between a D/A converter and a voltage comparator circuit and providing a level shift circuit for applying a voltage for compensating a voltage drop component caused by parasitic resistance to the plural capacitor circuits.
SOLUTION: By adding an offset correcting capacitor Coff parallel with a sample/hold capacitor CSH and impressing different voltages to the capacitors between a sampling term and a comparate term, the correction of ΔV is added to a D/A converting voltage Vdac so that an analog input voltage VAIN coincides with the D/A converting voltage Vdac which corresponds to the theoretically obtained A/D converting code of VAIN. Thus, an offset error uniformly included in the entire D/A converting voltage from the most significant bit to least significant bit of a D/A converting code is relatively shifted just for +ΔV or -ΔV so that offset correction is enabled.
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Inventors:
Yoshikazu Nagashima
Application Number:
JP1067899A
Publication Date:
December 13, 2006
Filing Date:
January 19, 1999
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03M1/38; H03M1/06; H03M1/46; (IPC1-7): H03M1/38
Domestic Patent References:
JP5110436A | ||||
JP8162955A | ||||
JP57202126A | ||||
JP2097123A | ||||
JP63004719A | ||||
JP7086947A | ||||
JP5160729A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai