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Title:
SUMMING ARITHMETIC PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPH0756891
Kind Code:
A
Abstract:

PURPOSE: To make a parallel execution of the correct summing arithmetic result even though the initial value of the summing arithmetic variable is not '0' by inserting an instruction order to initialize sum of the product arithmetic variables of each processor except one variable when the sum of the product arithmetic operations are parallely executed.

CONSTITUTION: The system is provided with a parallel summing arithmetic analysis part 31 to find out a loop part of the sum of product arithmetic operation part which is found by analyzing a source program, initializing instruction order generation part 31 generating the initializing instruction order to initialize '0' except one among the sum of the product arithmetic variables adding the sum of product arithmetic operation of each processor just before the loop part by remaining one of them, and summing instruction order generation part 33 where each processor generates the summing instruction order so as to obtain the total sum of the partial summing to be added to the sum of the product arithmetic variable after the instruction order obtaining the partial sum by added to the sum of the product arithmetic variable.


Inventors:
YAMANAKA EIJI
Application Number:
JP20545493A
Publication Date:
March 03, 1995
Filing Date:
August 20, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/45; G06F15/16; G06F17/10; (IPC1-7): G06F17/10; G06F9/45; G06F15/16
Attorney, Agent or Firm:
Morihiro Okada