Title:
SUPERCONDUCTIVE CIRCUIT CHIP
Document Type and Number:
Japanese Patent JPS60124979
Kind Code:
A
Abstract:
PURPOSE:To markedly reduce the variation in ground plane potential by a method wherein at least a ground terminal is provided in the neighborhood of a power source terminal, of chip terminals, closer to a circuit-loading region. CONSTITUTION:Each terminal is provided along the end surface 21 of the chip at the minimum terminal intervals P, and the power source terminal 3 is surrounded by ground terminals 4, 5, and 6. This terminal 6 is in a straight line passing through the terminal 3 and vertical to the end side 21, and is positioned inside the chip by P from the power source terminal. Then, the current supplied from the terminal 3 is supplied to the circuit inside the chip through a power source wiring 22 formed on the chip ground plane via insulator. The current grounded in this circuit returns to the neighborhood of the terminal 3 through broken-line arrows. Thereafter, the current flows toward ground terminals 4-10 and the like; however, the current directing inside the chip are mostly absorbed to the terminal 6, and current hardly flows to terminals 7-10 distant from the terminal 3. Therefore, the variation in potential due to floating inductance is markedly reduced.
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Inventors:
AOKI KATSUHIKO
TAZOU YASUO
YOSHIKIYO HARUO
TAZOU YASUO
YOSHIKIYO HARUO
Application Number:
JP23446783A
Publication Date:
July 04, 1985
Filing Date:
December 12, 1983
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L39/02; H01L27/18; (IPC1-7): H01L39/22
Other References:
J.APPL.PHYS=1983
Attorney, Agent or Firm:
Kugoro Tamamushi