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Patent Searching and Data


Title:
SURFACE TREATING METHOD FOR PRINTED CIRCUIT BOARD
Document Type and Number:
Japanese Patent JPH0548249
Kind Code:
A
Abstract:

PURPOSE: To prevent short circuit due to melting of a solder layer by selectively removing a solder-plated layer on various pattern except a solder plated later remaining pattern, and selectively covering the copper layer pattern exposed by etching the plated layer with a solder resist layer.

CONSTITUTION: A printed circuit board 6 having a through hole land pattern 11 of a two-layer structure of a copper layer 7 and a solder plated layer 9, and various patterns such as a foot-printed pattern 12 and a wiring pattern 13, is manufactured. An etching resist layer is selectively formed on the pattern to be retained with the layer 9 of the various patterns, and a dry film 15 is formed. With the film 15 as a mask only the layer 9 is selectively etched. Then, only the pattern 13 is heated by a printed circuit board 5 in which the layer 7 is exposed, and the solder of the layer 9 is melted. Soldering in which improper soldering scarcely occurs, can be performed at the time of mounting an electronic component.


Inventors:
MORITA YASUHIRO
Application Number:
JP20266291A
Publication Date:
February 26, 1993
Filing Date:
August 13, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H05K3/28; H05K3/42; (IPC1-7): H05K3/28; H05K3/42
Attorney, Agent or Firm:
Teiichi