Title:
SUSCEPTOR, HEAT TREATMENT AND HEAT TREATMENT METHOD
Document Type and Number:
Japanese Patent JP3586031
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the occurrence of a crystal defect in a semiconductor substrate at the time of executing heat treatment by making the semiconductor that at least at a heat treatment temperature in a state that the semiconductor substrate is loaded.
SOLUTION: When a film-like body 8 made of Si is loaded on a boat 2 so that it becomes a projecting form in an upper direction, the warp of the film-like body 8 reduces to 120μm with the self-weight of the film-like body 8. When the Si substrate whose diameter is 300mm and thickness is 725μm is loaded on the film-like body 8, the Si substrate 1 pushes down the film-like body 8 by 120μm by means of the weight of the Si substrate 1. Thus, the warp by means of the weight of the Si substrate 1 and the warp quantity (a) of the film-like body 8 are canceled, and the Si substrate 1 becomes plane. Since large stress is generated in the film-like body 8 in such a state, the semiconductor substrate 1 on the film-like body 8 is held almost horizontally in a state without the warp. Thus, stress hardly occurs in the semiconductor 1. Since the heat treatment of high temperature is executed in such a state, the defects of slip and the like do not occur.
Inventors:
View Yuichi
Akito Yamamoto
Akito Yamamoto
Application Number:
JP7218496A
Publication Date:
November 10, 2004
Filing Date:
March 27, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/683; C30B31/14; H01L21/00; H01L21/02; H01L21/205; H01L21/22; H01L21/31; H01L21/324; H01L21/673; H01L21/687; (IPC1-7): H01L21/68; H01L21/02; H01L21/22; H01L21/31; H01L21/324
Domestic Patent References:
| JP8008201A | ||||
| JP5102056A | ||||
| JP5235156A | ||||
| JP5114645A | ||||
| JP6333914A | ||||
| JP4059134U | ||||
| JP6275481A |
Attorney, Agent or Firm:
Takehiko Suzue