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Title:
SWITCH CIRCUIT
Document Type and Number:
Japanese Patent JPS6215922
Kind Code:
A
Abstract:

PURPOSE: To prevent tentative short-circuiting between inputs caused at switching and to suppress generation of noise by forming a switch in series connection of the 1st and 2nd transistors (TRs) in a circuit where the two switches are connected in series, one connecting terminal is used as an output terminal and the other connecting terminal is used as an input terminal.

CONSTITUTION: A N-channel MOS and a P-channel MOS are connected in series. A switch Swa is closed only when a switch control signal is at a high level and the inverse of signal is at a low level in the relation of the switching of switches Swa, Swb and the switch control signals , and the inverse of . On the other hand, the switch Swb is closed only when the signal is at a low level and the inverse of signal is at a high level. Thus, the switches Swa, Swb are both opened at a period when both the signals , and the inverse of are at high or low level caused tentatively by the delay between the signals and the inverse of , two inputs Vin1, Vin2 are not short-circuited and noise generated at an output Vout is suppressed.


Inventors:
IMAIZUMI EIKI
NAKATANI YUICHI
TSUKADA TOSHIRO
Application Number:
JP15404385A
Publication Date:
January 24, 1987
Filing Date:
July 15, 1985
Export Citation:
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Assignee:
HITACHI LTD
HITACHI VLSI ENG
International Classes:
H03K17/687; (IPC1-7): H03K17/687
Attorney, Agent or Firm:
Katsuo Ogawa



 
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