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Title:
SWITCHED CAPACITOR ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JPS60214086
Kind Code:
A
Abstract:

PURPOSE: To form a circuit into an IC capable of an optional processing by obtaining leading-out of the degree of amplification and control of the arithmetic function of the circuit by a ratio of clock frequencies for a switched capacitor equivalent resistance, a capacitor ratio, and clock control.

CONSTITUTION: In a circuit A, switches S1WS4 are controlled by clocks whose phases are opposite to phases of clocks used for control of switches S'1WS'4. In a circuit B, switches S1, S'2, S'3, and S4 are controlled by clocks whose phases are opposite to phases of clocks used for control of switches S'1, S2, S3, and S'4. Each time clocks and ' for the circuit B are changed when those for the circuit A are fixed, an operational amplifier output V0' is reduced by a value indicated by C2/C1.(-Vi). The operational amplifier output V0' is operated by the ratio of clock frequencies for the switched capacitor equivalent resistance and the capacitor ratio.


Inventors:
CHIBA TOMIO
KIDO MITSUYASU
KUDOU HIROYUKI
Application Number:
JP6903884A
Publication Date:
October 26, 1985
Filing Date:
April 09, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03H19/00; G06G7/12; G06G7/14; (IPC1-7): G06G7/14; H03H19/00
Attorney, Agent or Firm:
Akio Takahashi



 
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