PURPOSE: To reduce the definite GB product of an operational amplifier OP and to attain low power consumption by attaining addition with one operational amplifier, and forming a switched capacitor circuit.

CONSTITUTION: The circuit consists of a 1st coefficient circuit network AC where 1st unit blocks each comprising switched capacitors are arranged as a matrix, and a 2nd coefficient circuit network BC comprising similar 2nd unit blocks. Moreover, an adder OP is provided, which fetches an input signal to an input terminal via the 1st coefficient circuit network AC to calculate it and fetches the output signal from an output terminal to the input terminal via the 2nd coefficient circuit network BC to calculate it. Addition arrays of each coefficient in the 1st coefficient circuit network AC and the 2nd coefficient circuit network BC are arranged in the relation of realizing each coefficient of the transfer function of the entire circuit as to each column and each row and each unit block is formed in the circuit in response to the sign of each coefficient. Furthermore, switches are switched in a prescribed order with clock pulses more than the coefficients by a prescribed number. Thus, the number of operational amplifiers is decreased to attain power saving and high circuit integration and the effect of the definite GB produce is reduced.