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Title:
SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS5850817
Kind Code:
A
Abstract:

PURPOSE: To obtain an optional capacity value by connecting capacitors having a single capacity value and switches in a ladder shape, moving charges stored by an input signal, selecting an adequate combination of capacitors, and inputting them an operational amplifier at the same time.

CONSTITUTION: In (P+1)-number time zones (I0...IP) and a time zone I0 wherein (n+1)-number switches are turned on and off and a clock succeeds, all switches except switches S0 and Sn+2 are turned on to set all stored voltages to zero. In the time zone I1, the switches S0 and S1 are turned on to store an input voltage u(t1) from a node 20 in a capacitor C0. In the time zone I2, capacitors C0 and C1 are connected in parallel by turning on the switches S1 and S2 to charge the capacitors C0 and C1 to a voltage[C0/(C0+C1)]u(t1). Similarly, said operation is repeated and in a time zone Ip, ≥1 capacitor is selected to obtain an output at an output terminal G through the switch Sn+2.


Inventors:
MORI SHINSAKU
YAMAMOTO MASAHIRO
TANAKA MAMORU
Application Number:
JP14900481A
Publication Date:
March 25, 1983
Filing Date:
September 21, 1981
Export Citation:
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Assignee:
MORI SHINSAKU
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Domestic Patent References:
JPS5632816A1981-04-02
JPS56115019A1981-09-10
Attorney, Agent or Firm:
Yoshiyuki Osuge



 
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