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Title:
SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS61191111
Kind Code:
A
Abstract:

PURPOSE: To cancel the offset voltage of an operational amplifier without using an operational amplifier having a large through-rate by adding a delay feedback circuit in addition to a feedback circuit.

CONSTITUTION: The delay feedback circuit 4 charges an output with a clock pulse of an operational amplifier 1, applies the charged output at the next inverted clock pulse to an inverting input terminal 11 and forms a new feedback path. Then the offset voltage is charged to the capacitor of the feedback circuit 3 and the input circuit 2 at inverted phase clock pulse. This is canceled with the offset voltage at the terminal 11 at the next clock pulse . As a result, an output voltage not including the offset voltage is obtained from an output terminal 13 of the operational amplifier 1. Thus, it is not required to use an operational amplifier with a large through-rate.


Inventors:
WATANABE KENZO
FUJIWARA KAZUNOBU
Application Number:
JP2939385A
Publication Date:
August 25, 1986
Filing Date:
February 19, 1985
Export Citation:
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Assignee:
SANSHO CO
WATANABE KENZO
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Domestic Patent References:
JPS5632816A1981-04-02



 
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