Title:
SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS6126324
Kind Code:
A
Abstract:
PURPOSE: To decrease number of clock signals of a slide capacitor circuit by using a PMOS switch and an NMOS switch in mixture.
CONSTITUTION: When a clock signal is at a high level, NMOS TR switches 50-1 and 60-1 are turned on and PMOS TR switches 50-2, 60-2 are turned off. Thus, a capacitor 2 is charged through the NMOS switches 50-1, 60-1 with an input signal 1. When the signal goes to a low level, the NMOS switches 50-1, 60-1 are turned off, and the PMOS switches 50-2, 60-2 are turned on. Thus, charge of the capacitor 2 is transferred to a feedback capacitor 3 and an output signal 7 integrating an input signal 1 is obtained.
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Inventors:
FUKAZAWA SHIGERU
MATSUI KAZUMASA
MATSUI KAZUMASA
Application Number:
JP14684084A
Publication Date:
February 05, 1986
Filing Date:
July 17, 1984
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03K19/00; (IPC1-7): H03K19/00
Attorney, Agent or Firm:
Akio Takahashi
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