PURPOSE: To obtain a delay line having a small size and low cost with an easy control plus a steady delay time, by using a switched capacitor circuit and thus requiring no LC element.

CONSTITUTION: A switched capacitor delay line is formed by giving a multistage connection between the operational amplifying circuit A that has the sampling capacitor CA which samples the input voltage in a certain period and holds it plus the integral capacitor CB provided between the input and output terminals and then transfers the voltage held at the capacitor CA to the sampling capacitor of the next stage in a certain period and the circuit consisting of the switch S3 which discharges the residual electric charge of the capacitor CB in the circuit A. The delay time of such delay line is decided by the timing of the clock that actuates each contact.