PURPOSE: To reduce the effect of jitter caused by sampling an asynchronous input data by outputting a control signal in response to a jitter component and obtained through the comparison between a main sample value and a pseudo sample value.

CONSTITUTION: An interpolation control circuit 23 receives a high level interpolation request signal for a half period in succession to a change point of an input data when jitter is detected in an input data. Thus, a logic value of outputted interpolation control signals a, b is equal to a logic value of an input data supplied from a conversion circuit 21 only or the half period and a logic value of interpolation control signals b, c is inverted. Moreover, analog switches 3311, 3322 and 3321, 3312 are exclusively turned on in an interpolation circuit 24 in response to the interpolation control signals in such a way. Thus, the interpolation circuit implement a series of interpolation in which the state changes before and after the change in the input data as follows; the analog switches 3311, 3312 are ON, then only the analog switches 3321, 3312 are ON and then only the analog switches 3312, 3322 are ON.