PURPOSE: To surely decrease field-through noise by constituting the titled switched capacitor by a switching circuit where a couple of complementary MOS transistors (TRs) are connected in parallel, and a capacitor and varying the level amplitude of a clock depending on its frequency.

CONSTITUTION: A clock o whose level amplitude is controlled by a gain variable amplifier 4 is divided into a positive phase clock + and an opposite phase clock, inverse of by a phase inverting circuit 5 and given to a switched capacitor filter 1. In increasing the frequency of the clocks +, -, the frequency component of the field-through noise N is increased also sufficiently. Thus, the field-through noise N is suppressed sufficiently even with a coarse filter characteristic of a post filter 2. In decreasing the frequency of the clocks +, - conversely, the field-through noise N due to the harmonic component of the clocks +, - is decreased. Thus, the through-field noise N included in an output Sout is decreased up to a degree without practical problem.