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Patent Searching and Data


Title:
SWITCHED CAPACITOR INTEGRATION CIRCUIT
Document Type and Number:
Japanese Patent JPS60212021
Kind Code:
A
Abstract:

PURPOSE: To eliminate the effect of an offset voltage with simple constitution by constituting the circuit that a capacitor for differential voltage detection is charged by a voltage value between any input voltage and an offset voltage to any input voltage.

CONSTITUTION: Switches S1, S2 are interlocked so that the states as shown in the figures (A), (B) are repeated alternately. Thus, an electric charge of C1. (V2-Vofs) is stored in a capacitor CD for detecting a voltage difference at the period of (A), where Vofs is the offset voltage of an operational amplifier OP. Further, an electric charge of C1.(V1-Vofs) is stored in the capacitor CD for differential voltage detection at a period (B) and the electric charge difference C1.(V2-V1) between the periods is moved to the capacitor CI for difference voltage integration. As a result, the difference voltage of (C1/C2).(V2-V1) is stored in the difference voltage integration capacitor CI every switching of the switch and the accumulated voltage does not include the error component by the offset voltage Vofs at all.


Inventors:
WAKI OSAMU
KUNIEDA HIROAKI
Application Number:
JP6693384A
Publication Date:
October 24, 1985
Filing Date:
April 04, 1984
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Attorney, Agent or Firm:
Toshio Nakao