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Patent Searching and Data


Title:
SWITCHED CAPACITOR INTEGRATOR
Document Type and Number:
Japanese Patent JPS5985575
Kind Code:
A
Abstract:

PURPOSE: To decrease the capacity ratio of a capacity integrator by reducing gradually the voltage transferred to an integrated capacity connected between a negative input terminal and an output terminal of an operational amplifier with every operation of a switch which works on a clock decided by the digit number of a digital value notation number.

CONSTITUTION: When switches SW3 and 4 are turned on, the input signal voltage is sampled/held 2. This voltage is transferred with switches 5 and 6 turned on in the timing of a shorter cycle than a sampling clock S with the signal of weight coefficient of each digit of the digital value notation number delivered from a weight coefficient generator 3. Then the output voltage of an operational amplifier 1 is added to the so far output voltage in a ratio between capacities CA' and CB. Then switches SW7 and 8 are actuated with the timing clock equal to that of the generator 3 to discharge the electric charge of the capacity CB'. Thus the voltage of the capacity CB is set at one-to-sum value of capacities CB, and CB'. Then the voltage of a prescribed integration coefficient is delivered when the SW4 is turned on.


Inventors:
KATOU SEIJI
UENO NORIO
KANEKO KAZUHIRO
Application Number:
JP19551782A
Publication Date:
May 17, 1984
Filing Date:
November 08, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03H19/00; G06G7/186; (IPC1-7): G06G7/186; H03H19/00
Attorney, Agent or Firm:
Koshiro Matsuoka