PURPOSE: To obtain a sample-and-hold output in which an error voltage by a clock feed-through is compensated by cancelling the error voltage resulting from receiving a clock feed-through charge generated through a parasitic capacitance with a compensation circuit when the parasitic capacitance is in existence between a gate receiving a 1st clock and an inverting input terminal of an operational amplifier.

CONSTITUTION: A charge being a difference between a charging voltage V0(n-1/2)-Vi(n-1/2) of a capacitor 2 and an imaginary ground potential Va(n) being an inverting input terminal voltage of an operational amplifier 5 is discharged to a capacitor 14 through an analog switch 7 at a time t=nTs (Ts is a period) when a period of on-clock 1 is finished, where vi is an input voltage and vo is an output voltage. On the other hand, the charge in a capacitor 9 and a parasitic capacitance 12 of the analog switch is discharged to a capacitor 13. As a result, the relation of v0(n)=vi(n-1/2) is obtained and an error voltage by clock feed-through is cancelled and the result is outputted.