PURPOSE: To reduce the number of operational amplifiers and to obtain an analog delay line excellent in a noise characteristic by using a switched capacitor type amplifier instead of a sample holding circuit so as to use the operational amplifier in terms of time division multiplex.

CONSTITUTION: A switch 3 and switches 13 and 14 are turned on by the sampling slot of a clock 1. Accordingly a selector selects the signal to be delay of an input terminal IN. At this time,a switch 5 is turned on by the time slot of a clock A, and the 1st switched capacitor type amplifier (I) acts as a sample holding circuit and samples a signal from the terminal IN. This signal is supplied to the 2nd switched capacitor type amplifier (II) through a switch turned on by a clock Y. The amplifier II temporarily accumulates the output signal of the amplifier I at a clock B, and supplies the delayed signal to the selector in time except for the sampling slot. A switch 4 is turned on a clock X, and selects an output signal from the amplifier II. The selection output is inputted to the amplifier I and acts in the same manner.