PURPOSE: To reduce an input voltage by connecting a switched capacitor circuit in parallel, and shifting an charge of the capacitor successively to the next capacitor.
CONSTITUTION: S1 is turned on by one level of a clock pulse 1, an input voltage VIN is impressed to a capacitor C1. Subsequently, S1 is turned off by 1, and S3 is turned on by 3. In this way, a voltage of a C1 terminal can be set to VIN/2. Next, when S3 is turned off, and S4 is turned on by 4, a voltage of the C1 terminal can be set to VIN/10. In this way, a desired voltages can be obtained, therefore, S5 and S6 are turned on by 5, and a charge charged in C2 and C3 is discharged. Subsequently, S2 is turned on by 2, and desired VIN/10 is transferred to an output terminal. In this way, an input voltage an be reduced.
CHIBA TOMIO
KUDOU HIROYUKI
| JPS5883423A | 1983-05-19 |
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