To provide a high-speed dual-modulus prescaler circuit having a means for reducing the power consumption of the circuit.

The circuit is provided with a plurality of frequency bisectors of asynchronous types connected serially, a phase selector unit (11) inserted between two (10 and 12a) of these frequency bisectors and a control unit for supplying first control signals (S0, S1, S2, C1 and C2) to the selector unit as a function of a selected mode. The control unit receives four signals of phases mutually shifted at 90° from a first master/slave frequency divider and outputs one signal selected out of four phase-shifted signals. The selector unit is provided with a first amplifier branch (21) for receiving two first phase-shifted signals (F2I and F2Ib), a second amplifier branch (22) for receiving two second phase-shifted signals (F2Q and F2Qb) and a selection element (23) connected to the respective branches.